What Is Formal Verification?

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  • Written By: Andrew Kirmayer
  • Edited By: Shereen Skola
  • Last Modified Date: 13 November 2019
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Often used in the testing of computer circuits and software, formal verification is when the function of these systems is analyzed using mathematical formulas. In the case of developing software, the process is typically used to show whether the program is working properly, based on a pre-determined model. Sometimes the theoretical model is proven to be unsatisfactory. In addition to source code of software, formal verification can be used in developing combinational circuits, which are used to perform calculations in computers, as well as computer memory. The different approaches include after-the-fact verification, verification in parallel, and integrated verification in addition to various methods.

Mathematical procedures for calculations, called algorithms, are used in formal verification to test the functions of products at each stage of development. Software developers can find errors or bugs in both the source code and the model used to build it in the first place. Sometimes fundamental changes in how the code is being written can be made before a design error affects the end result. The verification step generally helps determine if the product is doing what was intended to do, and meets the specifications of the application it is for.


Formal verification can occur when a product is completed, which is called after-the-fact verification. A standard method, used throughout the design and development process, is not analyzed until the system is finished. Locating serious errors at this stage often leads to expensive and time-consuming revisions. Development and verification can also be carried out by two separate teams for verification in parallel. Through intercommunication, the developers can focus on independent tasks during the entire design process.

Integrated verification is when one team performs the development and the required assessment. Complex mathematical concepts are often used to verify the product’s capabilities along the way. Methods of formal verification vary among projects but one often used is model checking. A hardware or software model consists of various properties that designers want in the finished product. The model and the system can be periodically checked to see if properties match.

Another technique in formal verification involves using mathematical formulas and logic to represent a system and its properties. Rules defined in a formal system are generally found in the logic. Both of these techniques use various means to determine if a particular specification of a product is met. Developers can use different types of software in the formal verification process, each tailored to a specific system or programming language.


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