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Sequential logic (SL) in digital circuit theory is the set of rules and implementations of circuits that rely on the current and past events of logic states and transitions to determine present logic states. Knowing about combinational logic (CL), the set of rules and implementation of circuits that rely on the actual logic levels, reveals the key points in sequential logic. Logic levels for binary computing usually refer to high or low. In positive logic, 1 is high and 0 is low. Logic circuits are made up of gates that may have one or more inputs and usually only one output.
A simple CL gate is known as the buffer and the inverter or NOT gate. The buffer output is always the same as the input, but the inverter output is always not the input. Other gates used in CL include the AND gate, NAND gate, and NOR gate. The AND gate outputs a 1 only if both inputs are 1. The NAND gate and NOR gate are, respectively, an AND gate and an OR gate, each with an inverter at the output.
Sequential logic uses latches that lock the output levels based on previous output levels and current input levels. Latches are usually built using two partner gates, which are either two NAND or NOR gates. The gates of these latches, or flip-flops, are locked into one of two states by the gate outputs that are fed back to the input of the partner gate. By changing the levels on the free inputs of the gates, a reversal of logic level is achieved. Sequential logic analysis involves both observing the initial output levels and observing the change in output levels based on the change in input levels.
In binary counters, there is edge detection circuitry in the clock input for each binary digit (bit) latch. Counters usually use a positive-edge detect for normal count-up. For instance, an 8-bit counter uses 8-bit latches.
Sequential logic makes use of cascaded bit latches to produce an asynchronous (async) digital counter. When a bit from the less-significant-bit (LSB) latch is made to clock the more significant bit (MSB), it is known as an async counter. In async, latches clock each other at slightly different times, while synchronous (sync) logic clocks all latches simultaneously. The async counter will suffer a maximum total ripple delay equal to one latch ripple delay multiplied by the number of bits in the counter. In sync logic, the bit latches in a digital counter are clocked simultaneously, thus the total ripple delay is equal to one latch ripple delay for any number of bits in the counter.
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