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Power optimization is the attempt to reduce the power consumed by digital devices such as integrated circuits by balancing parameters like size, performance, and heat dissipation. It is a very critical area of electronic component design because many portable electronic devices require high processing capacity with low power consumption. The components need to perform complex functions yet generate as little heat and noise as possible, all packed onto a very tiny surface area. An intensively researched area of digital design, power optimization is vital to the commercial success of many devices.
The idea of optimizing power in electronic design began to gain attention in the late 1980s with the widespread use of portable devices. Battery life, heating effects, and cooling requirements became very important for both environmental and economical reasons. Fitting increasingly complex components onto smaller chip sizes became vital to ensure the production of smaller devices with more functionality. The heat generated by including so many components, however, became a major issue. Factors like device performance and reliability are also affected by heat.
To scale chips, reduce die size, and still have peak performance at acceptable temperature levels requires investing time in power optimization methodologies. Manually optimizing power becomes impossible with existing chips like integrated circuits because they contain millions of components. Typically, designers accomplish power optimization by limiting wasted energy, which is mostly speculation, architectural, and program waste. All these methods attempt to reduce energy wastage from the level of circuit design to execution and application.
Program waste occurs when a high-end microprocessor executes commands that are not necessary. Executing these commands does not change the contents of the memory and registers. Eliminating program waste means reducing the execution of dead instructions and getting rid of silent stores. Speculation waste happens when the processor fetches and executes instructions beyond unresolved branches. Architectural waste happens when structures like caches, branch predictors, and instruction queues are too large or too small.
Mostly designed to hold large amounts, architectural structures usually aren't used to their full capacity. Conversely, making them smaller also increases power consumption due to more misspeculation. Successful power optimization requires using a system level approach by selecting components that consume very little power. All possible combinations of these types of components can be explored in the design phase. Reducing the amount of switching activity needed in-circuit also ensures less power consumption.
Some of the other approaches used for power optimization include clock gating, sleep modes, and better logic design. Retiming, path balancing, and state encoding are other logic methods that can limit power consumption. Some microprocessor designers also use special formats to code design files that insert power-saving control features.
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